In modern CMOS microprocessors, an important new design obstacle has begun to emerge. Circuits cannot simply be optimized for delay—power consumption is now an additional critical parameter. In modern CMOS microprocessors, a significant portion of the power is dissipated in the clock distribution network, specifically in the local clock nets which drive the latches. With feature sizes decreasing and scale of integration increasing, this problem will continue to worsen. Thus, it can be concluded that improvements in clock distribution techniques, especially local clock distribution, have the potential to lead to major power savings in CMOS microprocessors.